Image sensors may be formed in various different architectures. For example, MOS type image sensors using column parallel architectures are shown in U.S. Pat. Nos. 6,115,065 and 6,787,749. Such a column parallel architecture connects each of the pixels in one column in parallel to one unit of the output circuit. During readout, one pixel in each column is selected at each time, and at the same time as all the other pixels in the same row. This allows reading out an entire row of image sensor elements simultaneously. The read-out information is converted to digital and output simultaneously.
The structure which carries out the image acquisition includes noise. The fixed components of the noise creates a fixed pattern noise. The A/D converters in the readout circuit may contribute to the fixed pattern noise.
Patents such as U.S. Pat. Nos. 6,304,826; 6,534,757 and 6,900,837 describe different ways to handle that noise. One technique may carry out a single calibration per A/D converter, and create a calibration level that represents an offset attributable to that A/D converter. That offset is used to compensate for the noise in the A/D converter. The calibration may be carried out, for example, per frame and per A/D converter. However, there is still a residual fixed pattern noise, and the differences between the frames may still be noticeable. Patents such as U.S. Pat. No. 6,900,837 suggest moving the pixel assignments to mix up the noise to make it less noticeable.